Microprocessors and microcontrollers form the core of electronic systems. Unfortunately, almost all the microprocessors and microcontrollers are imported, currently. IPs and patents with strict licensing terms protect their designs. Realizing the limitations of the processor industry, the SHAKTI Processor Program11 started as an academic initiative back in 2014. SHAKTI is an open source processor4 initiative by the Pratap Subramaniam–Center for Digital Intelligence and Secure Hardware Architecture (PC-CDISHA)–Reconfigurable Intelligent Systems Engineering (RISE) group, IIT-Madras. The project started with a generous grant from the Ministry of Electronics and Information Technology (MEITY), New Delhi.
The initiative is aimed to create open source, industrial-grade processors and build associated components of a more extensive ecosystem. This ecosystem is beyond these processor designs. Today, the SHAKTI program offers a software stack, FPGA prototypes, interconnect fabrics, accelerators, device IPs, verification suites, and more under a permissive open source license.
PS-CDISHA plans to realize at least three chips in silicon: the C-Class, I-Class, and a secure version of C-Class. The C-Class targets deep embedded and edge applications. The I-Class is targeted at Desktop and HPC-class applications. In addition, artificial intelligence/machine learning (AI/ML) accelerators are under active consideration. These are suitable for use in different applications such as smartcards, embedded systems, desktops, high-performance computing (HPC) systems, and various secured computing systems. A fault-tolerant version of SHAKTI is also in works.5 The secure version of the C-Class has hardware instruction-based security solutions. This shows the flexibility of using an instruction set that has no encumbrances thereby allowing free flow of design ideas into creative processor architectures.
RISC-V9 has been chosen as the instruction set architecture (ISA) for the SHAKTI class of processors. The SHAKTI processor and systems design is developed using the open source high-level synthesis (HLS) language: Bluespec System Verilog (BSV).1 BSV is an open source, high-level hardware description language. It provides a high-level abstraction, like going from assembly programming to C, and guarantees synthesizable circuits. Since the compiler does all the work for the designers, the design time for generating an instance is drastically reduced. Besides reducing design time, Bluespec enables users to work at a much higher level, increasing throughput. The language is now supported by an open source Bluespec compiler, which can generate a synthesizable Verilog for FPGA and ASIC targets.
C-Class is a member of the SHAKTI family of processors. It is a configurable and commercial-grade five-stage in-order core supporting the standard RV64GCSUN ISA extensions. The core generator in this repository can configure the core to generate a wide variety of design instances from the same high-level source code. The design instances can serve domains ranging from embedded systems, motor-control, IoT, storage, and industrial applications to low-cost, high-performance Linux-based applications. This flexibility helps in tuning the processor design instance for performance and power depending on the application needs. C-Class proof-of-concept designs enable the processor hardware to be customized for user-specific needs.
The source code for the C-Class is available under the open source permissive BSD license. The C-Class architecture has been tested in silicon in 22nm/180nm process technologies. There have been three major silicon implementations (also known as test tape-outs) of the SHAKTI C-Class—Rimo, Risecreek, and Moushik (see the accompanying figure).
Figure. The three major silicon implementations of the SHAKTI C-Class.
A software development kit is necessary for supporting the processor and the system on chip (SoC). The SHAKTI SDK, PS-CDISHA's software development kit, is an open source software development kit. It provides driver support for SPI, QSPI, PLIC, CLINT, UART, I2C, and PWM. It is developed with a clean separation between drivers, boot, core, and application layers.
The initiative is aimed to create open source, industrial-grade processors and build associated components of a more extensive ecosystem.
Multiple sensors have been connected and proven using the SHAKTI-SDK. Examples of these are available in a blog.10 This can be used as a starting point for software development. For working with the hardware, the SHAKTI website can be used.11 The software can be run in standalone or debug mode and supports multilevel logging, flash programming, and dynamic memory management.
The SDK serves as a single point for bare metal application development, projects, and benchmarks. In addition, support for third-party boards and in-house boards are available. Some operating systems supported by SHAKTI include Linux and FreeRTOS.3
To provide further impetus to the vital ecosystem of start-ups, innovators, and researchers in the country, MEITY announced the Swadeshi Microprocessor challenge12 in 2020 under AatmaNibharBharat Abhiyan. The challenge was opened to students at all levels and start-ups and demanded that contestants leverage Swadeshi processor IPs to innovate economical solutions for societal needs. The SHAKTI processor was also made available in open source for the technologists worldwide to design their own applications.
Approximately 6,170 teams with at least two members per team, including over 500 start-ups, competed during the initial stages of the challenge. They solved an online quiz and submitted an abstract and detailed proposal to reach the second stage. The participants were provided IPs ported on FPGA boards and financial and technical support to develop Hardware Proof of Concept applications around them.
Thirty teams with the most technically and financially viable solutions were selected and further given financial and technical assistance to improvise further on their hardware prototype and demonstrate. Out of the 30 teams, the 10 most innovative teams won the challenge with strategic solutions to various problems.
At a hardware level, security is becoming critical, given the ubiquity of technology we see today. An Intel study6 notes that organizations are increasingly looking for security features2 baked in at that hardware level. The SHAKTI program, recognizing the criticality of this need, is working on developing hardware-level security features. These include accelerators for encryption algorithms, side-channel resistant designs,8 data obfuscation, and other state-of-the-art features. In addition to the hardware, work is ongoing to provide secure boot functionalities to ensure only correctly verified software may run on a platform. Such a feature gains immense significance given over-the-air updates for edge devices.
Active research and development are being conducted for the hardware-level acceleration of AI algorithms, emphasizing edge inference. A systolic array-based accelerator is currently being developed for this purpose.
Today the SHAKTI microprocessor-based FPGA is running well over a year at the Indira Gandhi Centre for Atomic Research.7 This implementation provides security toward obsolescence of processors. The industry will be adopting SHAKTI in the next two years. Many of the start-ups such as SecurWeave14 and Mindgrove15 have put in special efforts to make SHAKTI class of processors marketable.
The major challenges in developing microprocessors are:
The SHAKTI Program perfectly echoes the "Atmanirbhar" ecosystem for the design, development, and production of microprocessors within India. The SHAKTI program has continuously demonstrated this by periodically taping out test SoCs. The winning teams at The Swadeshi Microprocessor Grand Challenge have adopted SHAKTI processor-based designs. The SHAKTI Program will continue to "Democratize and Promote India Specific SOC Design towards Self-Sustained Digital Technologies." Other than reduction of cost factor, since the SHAKTI design is in the open source, it enables start-ups to form an ecosystem and enhance their research and development capabilities in hardware, which has been elusive until date. There are other open source initiatives, such as SiFive;13 however, from a national security perspective, design of SHAKTI assumes significance.
Active research and development are being conducted for the hardware-level acceleration of AI algorithms, emphasizing edge inference.
Acknowledgment. The SHAKTI team was supported by funding provided by the Ministry of Electronics and Information Technology, Government of India for the design of the SHAKTI class of processors.
1. Bluespec Verilog; https://bluespec.com/
2. Das, S. et al. SHAKTI-MS: A RISC-V processor for memory safety in C. In Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, June 2019, 19–32).
3. FreeRTOS; https://www.freertos.org/
4. George, P. et al. SHAKTI: An Open-Source Processor Ecosystem.
5. Gupta, S., Gala, N., Madhusudan, G.S. and Kamakoti, V. SHAKTI-F: A fault tolerant microprocessor architecture. In Proceedings of the 2015 IEEE 24th Asian Test Symp. IEEE, Nov. 2015, 163–168.
6. Intel Study; https://intel.ly/3JjGOsc
7. IGCAR SHAKTI Implementation, 64; https://bit.ly/3vuo43u
8. KF, Muhammed Arsath., Ganesan, V., Bodduna, R., and Rebeiro, C. PARAM: A microprocessor hardened for power side-channel attack resistance. In Proceedings of the 2020 IEEE Intern. Symp. Hardware Oriented Security and Trust. IEEE, Dec. 2020, 23–34.
9. RISC-V International; https://riscv.org/
10. SHAKTI blogs; https://blogSHAKTI.org.in/
11. SHAKTI website; https://SHAKTI.org.in/
12. Swadeshi Microprocessor Challenge; https://bit.ly/3oO3lUN
13. SiFive; https://bit.ly/3Qsm7wT
14. SecurWeave; https://bit.ly/3JAFMZj
15. Mindgrove Technologies Private Limited; https://bit.ly/3JAFIZz
©2022 ACM 0001-0782/22/11
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and full citation on the first page. Copyright for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or fee. Request permission to publish from email@example.com or fax (212) 869-0481.
The Digital Library is published by the Association for Computing Machinery. Copyright © 2022 ACM, Inc.
No entries found