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Nanowires Key to Future Transistors, Electronics

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heterostructure nanowire

Researchers have grown nanowires with sharply defined layers of silicon and germanium, offering better transistor performance.

Credit: Purdue University / Seyet LLC

A major discovery by researchers at Purdue University; the University of California, Los Angeles; and IBM has brought the enablement of future ultrasmall transistors and more powerful computer chips using semiconducting nanowires a step closer to reality. The researchers have determined how to produce nanowires with sharply defined layers of different materials or heterostructures, in this case silicon and germanium.

Conventional transistors are manufactured on flat, horizontal silicon plates, while silicon nanowires are "grown" vertically. The vertical orientation could make it possible to fit more transistors on a chip, says Purdue professor Eric Stach.

The researchers first heated and melted particles of a gold-aluminum alloy in a vacuum chamber and then pumped in silicon gas so that the silicon would precipitate and form wires. Each wire was capped with a liquid gold-aluminum bead, and then the temperature was lowered to induce solidification of the caps, allowing the direct deposit of germanium onto the silicon. With the provision of such a heterostructure, a germanium gate can be created in each transistor.

The shrinkage of electronic devices made of conventional silicon-based semiconductors in order to continuously upgrade computing performance is becoming increasingly difficult to accomplish, and Stach speculates that the physical limits of silicon transistors will be reached within five to 10 years. Nanowire-based transistors are a potential solution to this problem.

From Purdue University News
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