Sign In

Communications of the ACM

ACM TechNews

Hp R&d Chief Shows Road to Terabyte Backplane

View as: Print Mobile App Share:
Prith Banerjee

HP Labs director Prith Banerjee

Credit: Thomas Archibald

New technologies will be the key to dealing with the coming flood of digital data, says Hewlett-Packard (HP) Labs director Prith Banerjee.

He says that in the future exascale computers will be powered by vast arrays of smartphone-class processors, and they will use board- and chip-level optical interconnects and large pools of HP's memristor non-volatile memories. "By 2020 your end customer will be living in a world where people access 50 zettabytes of data from 30 billion cell phones and 1.3 trillion sensors--and all that data will have to be analyzed by computer architectures you have to design," Banerjee says.

He describes a 30 GByte/s optical backplane HP created as a demo for its ProCruve 9200 switch. HP built the backplane from a hollow metal waveguide bundling 12 10 Gbyte/s optical channels, which cost as little as $10. Banerjee also cites multiple techniques, such as using more parallel lanes with more wavelengths, to deliver a terabyte/second optical backplane.

HP sees longer-term projects in areas such as silicon photonics and free-space optics that hold promise for chip-level interfaces and photonic processing.

From EE Times 
View Full Article

Abstracts Copyright © 2012 Information Inc. External Link, Bethesda, Maryland, USA 


No entries found

Sign In for Full Access
» Forgot Password? » Create an ACM Web Account